Issued Patents 2017
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9735159 | Optimized layout for relaxed and strained liner in single stress liner technology | Younsung Choi | 2017-08-15 |
| 9659934 | Methods and apparatus for quantum point contacts in CMOS processes | Henry Litzmann Edwards | 2017-05-23 |
| 9543374 | Low temperature coefficient resistor in CMOS flow | Kamel Benaissa, Sarah Liu, Song Zhao | 2017-01-10 |
| 9543437 | Integrated circuit with dual stress liner boundary | Youn Sung Choi | 2017-01-10 |