Issued Patents 2017
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9779200 | Methods for multi-wire routing and apparatus implementing same | Daryl Fox | 2017-10-03 |
| 9754878 | Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires | Stephen Kornachuk, James Mali, Carole Lambert, Brian Reed | 2017-09-05 |
| 9741719 | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits | Michael C. Smayling | 2017-08-22 |
| 9711495 | Oversized contacts and vias in layout defined by linearly constrained topology | — | 2017-07-18 |
| 9704845 | Methods for linewidth modification and apparatus implementing the same | Michael C. Smayling | 2017-07-11 |
| 9673825 | Circuitry and layouts for XOR and XNOR logic | — | 2017-06-06 |
| 9633987 | Integrated circuit cell library for multiple patterning | Michael C. Smayling | 2017-04-25 |
| 9595515 | Semiconductor chip including integrated circuit defined within dynamic array section | Michael C. Smayling | 2017-03-14 |
| 9589091 | Scalable meta-data objects | Michael C. Smayling, Daryl Fox, Jonathan R. Quandt | 2017-03-07 |
| 9563733 | Cell circuit and layout with linear finfet structures | — | 2017-02-07 |
| 9536899 | Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same | Jim Mali, Carole Lambert | 2017-01-03 |