Issued Patents 2017
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9817928 | Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits | Victor Moroz | 2017-11-14 |
| 9817059 | Evaluation of thermal instability stress testing | Thu Nguyen, Tzong-Kwang Henry Yeh, Shih-Yao Christine Sun, Raymond Leung | 2017-11-14 |
| 9742406 | Circuit skew compensation trigger system | Thu Nguyen, Raymond Leung | 2017-08-22 |
| 9735227 | 2D material super capacitors | Victor Moroz | 2017-08-15 |
| 9728528 | Method and apparatus for floating or applying voltage to a well of an integrated circuit | Victor Moroz, James David Sproch, Robert B. Lefferts | 2017-08-08 |
| 9691764 | FinFET cell architecture with power traces | Victor Moroz, Deepak D. Sherlekar | 2017-06-27 |
| 9691768 | Nanowire or 2D material strips interconnects in an integrated circuit cell | Victor Moroz | 2017-06-27 |