Issued Patents 2017
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9847248 | Method of making a stacked device assembly | Frederick A. Ware, Ely Tsern | 2017-12-19 |
| 9824730 | Memory components and controllers that calibrate multiphase synchronous timing references | Thomas J. Giovannini, Scott C. Best, Lei Luo | 2017-11-21 |
| 9734921 | Memory repair using external tags | Frederick A. Ware, Suresh Rajan | 2017-08-15 |
| 9734879 | Memory device comprising programmable command-and-address and/or data interfaces | Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal +2 more | 2017-08-15 |
| 9734112 | Memory with alternative command interfaces | Liji Gopalakrishnan, Yi Lu | 2017-08-15 |
| 9721629 | On-die termination of address and command signals | Kyung Suk Oh | 2017-08-01 |
| 9721630 | Strobe acquisition and tracking | Bret G. Stott, Frederick A. Ware, Yuanlong Wang | 2017-08-01 |
| 9704560 | Memory component with staggered power-down exit | Lei Luo, Liji Gopalakrishnan | 2017-07-11 |
| 9705498 | On-die termination | — | 2017-07-11 |
| 9703503 | Reconfigurable memory system data strobes | Frederick A. Ware, Craig E. Hampel | 2017-07-11 |
| 9691447 | Memory controller with staggered request signal output | Bret G. Stott, Benedict Lau | 2017-06-27 |
| 9691454 | Memory controller with phase adjusted clock for performing memory operations | Lei Luo | 2017-06-27 |
| 9666250 | Memory signal buffers and modules supporting variable access granularity | — | 2017-05-30 |
| 9665507 | Protocol including a command-specified timing reference signal | Thomas J. Giovannini | 2017-05-30 |
| 9660648 | On-die termination control | Kyung Suk Oh | 2017-05-23 |
| 9652409 | Memory access during memory calibration | Frederick A. Ware | 2017-05-16 |
| 9632956 | Expandable asymmetric-channel memory system | Arun Vaidyanath, Sanku Mukherjee | 2017-04-25 |
| 9575835 | Error correction in a memory device | Thomas Vogelsang, Suresh Rajan, Frederick A. Ware, Wayne F. Ellis | 2017-02-21 |
| 9570129 | On-die termination of address and command signals | Kyung Suk Oh | 2017-02-14 |
| 9570126 | Memory with deferred fractional row activation | James E. Harris, Thomas Vogelsang, Frederick A. Ware | 2017-02-14 |
| 9563228 | Clock generation for timing communications with ranks of memory devices | Jared L. Zerbe, John Eble | 2017-02-07 |
| 9563583 | Memory system topologies including a buffer device and an integrated circuit memory device | Ely Tsern, Craig E. Hampel | 2017-02-07 |
| 9552865 | Method and apparatus for calibrating write timing in a memory system | Thomas J. Giovannini, Alok Gupta, Steven C. Woo | 2017-01-24 |