Issued Patents 2017
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9659886 | Method of fabricating semiconductor device having voids between top metal layers of metal interconnects | Chung-Hsin Lin, Ping-Heng Wu, Chao-Wen Lay, Ying-Cheng Chuang | 2017-05-23 |
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9659886 | Method of fabricating semiconductor device having voids between top metal layers of metal interconnects | Chung-Hsin Lin, Ping-Heng Wu, Chao-Wen Lay, Ying-Cheng Chuang | 2017-05-23 |