Issued Patents 2017
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9784790 | Method for testing through silicon vias in 3D integrated circuits | — | 2017-10-10 |
| 9588174 | Method for testing through silicon vias in 3D integrated circuits | — | 2017-03-07 |
| 9568540 | Method for the characterization and monitoring of integrated circuits | Peilin Song, Franco Stellari | 2017-02-14 |