| 9721856 |
Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage |
Karl R. Erickson, Phil C. Paone, John E. Sheets, II, Gregory J. Uhlmann |
2017-08-01 |
| 9712170 |
Level-shifting latch |
Anthony Gus Aipperspach, Steven J. Baumgartner, Charles P. Geer, David W. Siljenberg, Alan P. Wagstaff |
2017-07-18 |
| 9685526 |
Side gate assist in metal gate first process |
Karl R. Erickson, Phil C. Paone, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams |
2017-06-20 |
| 9666305 |
System for testing charge trap memory cells |
Karl R. Erickson, Phil C. Paone, John E. Sheets, II, Gregory J. Uhlmann |
2017-05-30 |
| 9646712 |
Implementing eFuse visual security of stored data using EDRAM |
Todd A. Christensen, Karl R. Erickson, Phil C. Paone, John E. Sheets, II, Gregory J. Uhlmann |
2017-05-09 |
| 9589653 |
Creating default states for non-volatile memory elements |
Karl R. Erickson, Robert E. Kilker, Phil C. Paone, Gregory J. Uhlmann |
2017-03-07 |
| 9589639 |
Multiple FET non-volatile memory with default logical state |
Karl R. Erickson, Robert E. Kilker, Phil C. Paone, John E. Sheets, II, Gregory J. Uhlmann |
2017-03-07 |
| 9583403 |
Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage |
Karl R. Erickson, Phil C. Paone, John E. Sheets, II, Gregory J. Uhlmann |
2017-02-28 |
| 9570193 |
Implementing hidden security key in eFuses |
Karl R. Erickson, Phil C. Paone, John E. Sheets, II, Gregory J. Uhlmann |
2017-02-14 |
| 9553584 |
Level-shifting latch |
Anthony Gus Aipperspach, Steven J. Baumgartner, Charles P. Geer, David W. Siljenberg, Alan P. Wagstaff |
2017-01-24 |
