| 9721856 |
Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage |
Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II |
2017-08-01 |
| 9685526 |
Side gate assist in metal gate first process |
Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Kelly L. Williams |
2017-06-20 |
| 9666305 |
System for testing charge trap memory cells |
Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II |
2017-05-30 |
| 9646712 |
Implementing eFuse visual security of stored data using EDRAM |
Todd A. Christensen, Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II |
2017-05-09 |
| 9589653 |
Creating default states for non-volatile memory elements |
Karl R. Erickson, Robert E. Kilker, Phil C. Paone, David P. Paulsen |
2017-03-07 |
| 9589639 |
Multiple FET non-volatile memory with default logical state |
Karl R. Erickson, Robert E. Kilker, Phil C. Paone, David P. Paulsen, John E. Sheets, II |
2017-03-07 |
| 9583403 |
Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage |
Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II |
2017-02-28 |
| 9570193 |
Implementing hidden security key in eFuses |
Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II |
2017-02-14 |
