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Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform |
Gad Sheaffer, Ronny Ronen, Eliezer Weissmann |
2017-08-29 |
| 9727476 |
2-D gather instruction and a 2-D cache |
Oleg Margulis |
2017-08-08 |
| 9720730 |
Providing an asymmetric multicore processor system transparently to an operating system |
Ilya Osadchiy, Ronny Ronen, Eliezer Weissmann, Michael Mishaeli, Alon Naveh +13 more |
2017-08-01 |
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Systems, apparatuses, and methods for performing a horizontal partial sum in response to a single instruction |
Elmoustapha Ould-Ahmed-Vall, Moustapha Hagog, Robert Valentine, Amit Gradstein, Simon Rubanovich +2 more |
2017-06-13 |
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CPU/GPU synchronization mechanism |
Esfirush Natanzon, Ilya Osadchiy, Yoav Zach |
2017-04-25 |
| 9552207 |
Method and apparatus for performance efficient ISA virtualization using dynamic partial binary translation |
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2017-01-24 |