Issued Patents 2017
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9747225 | Interrupt controller | Tolga Ozguner, Elene Terry, Jonathan Ross | 2017-08-29 |
| 9710878 | Low power DMA labeling | Ryan Scott Haraden, Matthew R. Tubbs, Adam J. Muff | 2017-07-18 |
| 9710274 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-07-18 |
| 9678885 | Regular expression memory region with integrated regular expression engine | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-06-13 |
| 9652238 | Instruction set architecture with opcode lookup using memory attribute | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-05-16 |
| 9652239 | Instruction set architecture with opcode lookup using memory attribute | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-05-16 |
| 9632786 | Instruction set architecture with extended register addressing using one or more primary opcode bits | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-04-25 |
| 9632779 | Instruction predication using instruction filtering | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-04-25 |
| 9619234 | Indirect instruction predication | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-04-11 |
| 9606841 | Thread scheduling across heterogeneous processing elements with resource mapping | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2017-03-28 |
| 9600346 | Thread scheduling across heterogeneous processing elements with resource mapping | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2017-03-21 |
| 9594562 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-03-14 |
| 9594557 | Floating point execution unit for calculating packed sum of absolute differences | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-03-14 |
| 9594556 | Floating point execution unit for calculating packed sum of absolute differences | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-03-14 |
| 9582277 | Indirect instruction predication | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-02-28 |
| 9549100 | Low-latency timing control | Jonathan Ross, Elene Terry | 2017-01-17 |
| 9542184 | Local instruction loop buffer utilizing execution unit register file | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-01-10 |