Issued Patents 2017
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9791507 | Customer-transparent logic redundancy for improved yield | Igor Arsovski, Eric D. Hunt-Schroeder, Andrew K. Killorin | 2017-10-17 |
| 9760673 | Application specific integrated circuit (ASIC) test screens and selection of such screens | Eric D. Hunt-Schroeder, Igor Arsovski, Paul J. Grzymkowski | 2017-09-12 |
| 9653330 | Threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binning | Jeanne P. Bickford, Robert McMahon, Troy J. Perry, Thomas G. Sopchak | 2017-05-16 |