Issued Patents 2017
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9791507 | Customer-transparent logic redundancy for improved yield | John R. Goss, Eric D. Hunt-Schroeder, Andrew K. Killorin | 2017-10-17 |
| 9759767 | Pre-test power-optimized bin reassignment following selective voltage binning | Jeanne P. Bickford, Paul J. Grzymkowski, Susan K. Lichtensteiger, Robert McMahon, Troy J. Perry +2 more | 2017-09-12 |
| 9760673 | Application specific integrated circuit (ASIC) test screens and selection of such screens | Eric D. Hunt-Schroeder, John R. Goss, Paul J. Grzymkowski | 2017-09-12 |
| 9704575 | Content-addressable memory having multiple reference matchlines to reduce latency | Michael T. Fragano, Robert M. Houle, Thomas M. Maffitt | 2017-07-11 |
| 9601200 | TCAM structures with reduced power supply noise | Michael T. Fragano, Thomas M. Maffitt | 2017-03-21 |
| 9583192 | Matchline precharge architecture for self-reference matchline sensing | Michael T. Fragano, Thomas M. Maffitt, Robert M. Houle | 2017-02-28 |
| 9542981 | Self-timed, single-ended sense amplifier | Travis R. Hebig | 2017-01-10 |