Issued Patents 2017
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9762213 | Initializing scannable and non-scannable latches from a common clock buffer | William V. Huott, Ricardo H. Nigaglioni, Hagen Schmidt | 2017-09-12 |
| 9762212 | Initializing scannable and non-scannable latches from a common clock buffer | William V. Huott, Ricardo H. Nigaglioni, Hagen Schmidt | 2017-09-12 |
| 9760665 | Validating variation of timing constraint measurements | Sachin Gupta, Vasant Rao, Suriya T. Skariah, James E. Sundquist | 2017-09-12 |
| 9760664 | Validating variation of timing constraint measurements | Sachin Gupta, Vasant Rao, Suriya T. Skariah, James E. Sundquist | 2017-09-12 |
| 9720035 | Performance-screen ring oscillator (PSRO) using an integrated circuit test signal distribution network | — | 2017-08-01 |
| 9664735 | Debugging scan latch circuits using flip devices | — | 2017-05-30 |
| 9618580 | Debugging scan latch circuits using flip devices | — | 2017-04-11 |
| 9614507 | Programmable delay circuit including hybrid fin field effect transistors (finFETs) | Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan | 2017-04-04 |
| 9575529 | Voltage droop reduction in a processor | Brian W. Curran, Preetham M. Lobo, Richard F. Rizzolo, Tobias Webel | 2017-02-21 |
| 9552455 | Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications | Daniel J. Poindexter, Gregory G. Freeman, Siyuranga O. Koswatta, J. Campbell Scott, Leon Sigal | 2017-01-24 |
| 9543463 | Signal distribution in integrated circuit using optical through silicon via | Effendi Leobandung, Dieter Wendel | 2017-01-10 |
| 9543935 | Programmable delay circuit including hybrid fin field effect transistors (finFETs) | Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan | 2017-01-10 |