Issued Patents 2017
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852259 | Area and/or power optimization through post-layout modification of integrated circuit (IC) design blocks | Jeanne P. Bickford, Alok Chandra, Anand Kumaraswamy, Sandeep Prajapati | 2017-12-26 |
| 9767240 | Temperature-aware integrated circuit design methods and systems | Jeanne P. Bickford, Alok Chandra, Anand Kumaraswamy, Sandeep Prajapati | 2017-09-19 |
| 9740815 | Electromigration-aware integrated circuit design methods and systems | Jeanne P. Bickford, Alok Chandra, Anand Kumaraswamy, Sandeep Prajapati | 2017-08-22 |
| 9571111 | System and method to speed up PLL lock time on subsequent calibrations via stored band values | Hayden C. Cranford, Jr., Rajesh Agraramachandrarao, Sandeep Niranjan Tippannanavar, Neelamekakannan Alagarsamy | 2017-02-14 |