Issued Patents 2017
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9754829 | Self-aligned conductive polymer pattern placement error compensation layer | Erik Robert Hosler | 2017-09-05 |
| 9748176 | Pattern placement error compensation layer in via opening | Erik Robert Hosler | 2017-08-29 |
| 9704807 | Pattern placement error compensation layer | Erik Robert Hosler | 2017-07-11 |
| 9633942 | Conductively doped polymer pattern placement error compensation layer | Erik Robert Hosler | 2017-04-25 |
| 9576097 | Methods for circuit pattern layout decomposition | Elise Laffosse | 2017-02-21 |