Issued Patents 2017
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9818642 | Method of forming inter-level dielectric structures on semiconductor devices | Mehul D. Shroff | 2017-11-14 |
| 9685405 | Fuse/resistor utilizing interconnect and vias and method of making | Mehul D. Shroff, Edward O. Travis | 2017-06-20 |
| 9652577 | Integrated circuit design using pre-marked circuit element object library | Edward O. Travis, Ertugrul Demircan, Michael A. Stockinger | 2017-05-16 |
| 9640430 | Semiconductor device with graphene encapsulated metal and method therefor | Mehul D. Shroff | 2017-05-02 |
| 9601354 | Semiconductor manufacturing for forming bond pads and seal rings | Sergio A. Ajuria, Phuc M. Nguyen | 2017-03-21 |
| 9548266 | Semiconductor package with embedded capacitor and methods of manufacturing same | Sergio A. Ajuria, Phuc M. Nyugen | 2017-01-17 |