| 9847116 |
Circuit and method for controlling MRAM cell bias voltages |
Dietmar Gogl, Thomas Andre |
2017-12-19 |
| 9740431 |
Memory controller and method for interleaving DRAM and MRAM accesses |
Thomas Andre, Dietmar Gogl |
2017-08-22 |
| 9734884 |
Method for writing to a magnetic tunnel junction device |
Thomas Andre |
2017-08-15 |
| 9697880 |
Self-referenced read with offset current in a memory |
Thomas Andre, Chitra Subramanian |
2017-07-04 |
| 9697879 |
Memory device with shared read/write circuitry |
Chitra Subramanian |
2017-07-04 |
| 9691442 |
Memory device with reduced on-chip noise |
Thomas Andre, Dietmar Gogl |
2017-06-27 |
| 9679627 |
Write verify programming of a memory device |
Thomas Andre, Dimitri Houssameddine, Jon Slaughter, Chitra Subramanian |
2017-06-13 |
| 9601175 |
Word line auto-booting in a spin-torque magnetic memory having local source lines |
Thomas Andre |
2017-03-21 |
| 9583169 |
Boosted supply voltage generator and method therefore |
Dietmar Gogl, Thomas Andre, Halbert S. Lin |
2017-02-28 |
| 9575125 |
Memory device with reduced test time |
Thomas Andre, William Meadows |
2017-02-21 |
| 9569640 |
Tamper detection and response in a memory device |
Chitra Subramanian, Halbert S. Lin, Thomas Andre |
2017-02-14 |
| 9552863 |
Memory device with sampled resistance controlled write voltages |
Thomas Andre, Chitra Subramanian, Dietmar Gogl |
2017-01-24 |
| 9552849 |
Memory device with timing overlap mode and precharge timing circuit |
Thomas Andre, Halbert S. Lin |
2017-01-24 |
| 9542989 |
Circuit and method for controlling MRAM cell bias voltages |
Dietmar Gogl, Thomas Andre |
2017-01-10 |
| 9543041 |
Configuration and testing for magnetoresistive memory to ensure long term continuous operation |
Jason Janesky, Dimitri Houssameddine, Mark Deherrera |
2017-01-10 |