Issued Patents 2017
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9689918 | Test access architecture for stacked memory and logic dies | Wu-Tung Cheng, Ruifeng Guo, Yu Huang, Liyang Lai, Etienne Racine +3 more | 2017-06-27 |
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9689918 | Test access architecture for stacked memory and logic dies | Wu-Tung Cheng, Ruifeng Guo, Yu Huang, Liyang Lai, Etienne Racine +3 more | 2017-06-27 |