MG

Marcus Vinicius da Mata Gomes

CS Cadence Design Systems: 2 patents #21 of 238Top 9%
📍 San Jose, CA: #1,429 of 5,952 inventorsTop 25%
🗺 California: #13,043 of 60,394 inventorsTop 25%
Overall (2017): #127,750 of 506,227Top 30%
2
Patents 2017

Issued Patents 2017

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
9633151 Methods, systems, and computer program product for verifying electronic designs with clock domain crossing paths Xiaoyang Sun, Andrea Iabrudi Tavares, Lawrence Loh, Fabiano Peixoto 2017-04-25
9594861 Method and system to perform equivalency checks Antonio Celso Caldeira, Jr., Lawrence Loh 2017-03-14