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Jeffrey S. Salowe

CS Cadence Design Systems: 2 patents #21 of 238Top 9%
📍 Los Gatos, CA: #184 of 660 inventorsTop 30%
🗺 California: #13,043 of 60,394 inventorsTop 25%
Overall (2017): #141,709 of 506,227Top 30%
2
Patents 2017

Issued Patents 2017

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
9817941 Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs Satish Raj, Mark Rossman 2017-11-14
9754072 Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques Satish Raj, Olivier Pribetich, Karun Sharma, Yinnie Lee, Gary Matsunami 2017-09-05