Issued Patents 2017
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 9685969 | Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration | Adesh Garg, Anand J. Vasani, Hyo Gyuem Rhew, Jiawen Zhang, Jun Cao +3 more | 2017-06-20 | $87,430,000 |