Issued Patents 2017
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9734272 | Techniques for generating physical layouts of in silico multi mode integrated circuits | Lawrence T. Clark, Dan Patterson, Srivatsan Chellappa | 2017-08-15 |
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9734272 | Techniques for generating physical layouts of in silico multi mode integrated circuits | Lawrence T. Clark, Dan Patterson, Srivatsan Chellappa | 2017-08-15 |