JD

James E. DeMaris

CS Cadence Design Systems: 1 patents #55 of 238Top 25%
📍 Battle Ground, WA: #7 of 20 inventorsTop 35%
🗺 Washington: #4,569 of 12,901 inventorsTop 40%
Overall (2017): #389,776 of 506,227Top 80%
1
Patents 2017

Issued Patents 2017

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
9772668 Power shutdown with isolation logic in I/O power domain Tobing Soebroto, Jose L. Medero, Scott J. Tucker 2017-09-26