| 9507597 |
Selective accumulation and use of predicting unit history |
Terry Parks, John Michael Greer |
2016-11-29 |
| 9501286 |
Microprocessor with ALU integrated into load unit |
Gerard M. Col, Colin Eddy |
2016-11-22 |
| 9483406 |
Communicating prefetchers that throttle one another |
John Michael Greer |
2016-11-01 |
| 9483263 |
Uncore microcode ROM |
G. Glenn Henry, Terry Parks, John Bunda, Brent Bean |
2016-11-01 |
| 9389863 |
Processor that performs approximate computing instructions |
G. Glenn Henry, Terry Parks |
2016-07-12 |
| 9378019 |
Conditional load instructions in an out-of-order execution microprocessor |
G. Glenn Henry, Terry Parks, Gerard M. Col, Colin Eddy |
2016-06-28 |
| 9317301 |
Microprocessor with boot indicator that indicates a boot ISA of the microprocessor as either the X86 ISA or the ARM ISA |
G. Glenn Henry, Terry Parks |
2016-04-19 |
| 9317288 |
Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline |
G. Glenn Henry, Terry Parks |
2016-04-19 |
| 9274795 |
Conditional non-branch instruction prediction |
G. Glenn Henry, Terry Parks |
2016-03-01 |
| 9251083 |
Communicating prefetchers in a microprocessor |
John Michael Greer |
2016-02-02 |
| 9244686 |
Microprocessor that translates conditional load/store instructions into variable number of microinstructions |
G. Glenn Henry, Terry Parks, Gerard M. Col, Colin Eddy |
2016-01-26 |