Issued Patents 2016
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9529045 | Taps with class T0-T2, T4 capabilities and topology selection logic | — | 2016-12-27 |
| 9523738 | TCK/TMS(C) counter circuitry with third, fourth count and reset outputs | — | 2016-12-20 |
| 9497097 | Inserting sequence numbers into data blocks merged from data streams | — | 2016-11-15 |
| 9494648 | Comparator with load signal output connected to timestamp value register | — | 2016-11-15 |
| RE46193 | Distributed power control for controlling power consumption based on detected activity of logic blocks | Timothy David Anderson, Lewis Nardini, Jose Luis Flores, Abhijeet Ashok Chachad, Raguram Damodaran +1 more | 2016-11-01 |
| 9423458 | Transporting ordered test data, mode select, ready, precharge packet bits | — | 2016-08-23 |
| 9423459 | Taps with class T0-T2 and T3, T4(W), and T5(W) capabilities | — | 2016-08-23 |
| 9395413 | Blocking the effects of scan chain testing upon a change in scan chain topology | Robert A. McGowan | 2016-07-19 |
| 9342468 | Memory time stamp register external to first and second processors | Oliver P. Sohm, Brian Cruickshank, Manisha Agarwala | 2016-05-17 |
| 9310434 | Scan topology discovery in target systems | — | 2016-04-12 |
| 9285426 | Blocking the effects of scan chain testing upon a change in scan chain topology | Robert A. McGowan | 2016-03-15 |
| 9267990 | CLK/TMS counter having reset output coupled to fourth count output | — | 2016-02-23 |
| 9239748 | Comparator circuitry coupled to first, second time stamp overlap bits | — | 2016-01-19 |