Issued Patents 2016
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9524902 | Method of forming integrated circuit with conductive line having line-ends | Pei-Wen Huang, Jyu-Horng Shieh | 2016-12-20 |
| 9502287 | Method of preventing pattern collapse | Chung-Wen Wu, Jeng-Shiou Chen, Jang-Shiang Tsai, Jyu-Horng Shieh | 2016-11-22 |
| 9496224 | Semiconductor device having air gap structures and method of fabricating thereof | Jyu-Horng Shieh | 2016-11-15 |
| 9472448 | Contact plug without seam hole and methods of forming the same | Jyu-Horng Shieh | 2016-10-18 |
| 9437541 | Patterning approach to reduce via to via minimum spacing | Chung-Wen Wu | 2016-09-06 |
| 9412650 | Interconnect structure and method of forming the same | Jeng-Shiou Chen | 2016-08-09 |
| 9406589 | Via corner engineering in trench-first dual damascene process | — | 2016-08-02 |
| 9401329 | Interconnect structure and method of forming the same | Jeng-Shiou Chen, Jyu-Horng Shieh, Minghsing Tsai | 2016-07-26 |
| 9397047 | Interconnect structure and method of forming the same | Jeng-Shiou Chen, Jyu-Horng Shieh, Ming-Hsing Tsai | 2016-07-19 |
| 9312222 | Patterning approach for improved via landing profile | Chung-Wen Wu | 2016-04-12 |
| 9287212 | Semiconductor device interconnection structure having dielectric-filled notches | Chung-Wen Wu | 2016-03-15 |
| 9257298 | Systems and methods for in situ maintenance of a thin hardmask during an etch process | Chung-Wen Wu | 2016-02-09 |