Victor Moroz — 11 Patents at Synopsys

Issued Patents 2016

Showing 1–11 of 11 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
9472423	Method for suppressing lattice defects in a semiconductor substrate	Dipankar Pramanik	2016-10-18	$6,230,000
9465897	Analysis of stress impact on transistor performance	Dipankar Pramanik	2016-10-11	$11,062,000
9418189	SRAM layouts	Xi-Wei Lin	2016-08-16	$9,352,000
9400862	Cells having transistors and interconnects including nanowires or 2D material strips	Jamil Kawa	2016-07-26	$30,706,000
9379018	Increasing Ion/Ioff ratio in FinFETs and nano-wires	Munkang Choi, Xi-Wei Lin	2016-06-28	$7,635,000
9378320	Array with intercell conductors including nanowires or 2D material strips	Jamil Kawa	2016-06-28	$7,635,000
9379183	Methods for manufacturing integrated circuit devices having features with reduced edge curvature	Lars Bomholt	2016-06-28	$7,635,000
9361418	Nanowire or 2D material strips interconnects in an integrated circuit cell	Jamil Kawa	2016-06-07	$10,616,000
9287253	Method and apparatus for floating or applying voltage to a well of an integrated circuit	Jamil Kawa, James David Sproch, Robert B. Lefferts	2016-03-15	$5,443,000
9275182	Placing transistors in proximity to through-silicon vias	James David Sproch, Xiaopeng Xu, Aditya Pradeep Karmarkar	2016-03-01	$12,421,000
9257429	N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch	Deepak D. Sherlekar	2016-02-09	$12,508,000