| 9472423 |
Method for suppressing lattice defects in a semiconductor substrate |
Dipankar Pramanik |
2016-10-18 |
| 9465897 |
Analysis of stress impact on transistor performance |
Dipankar Pramanik |
2016-10-11 |
| 9418189 |
SRAM layouts |
Xi-Wei Lin |
2016-08-16 |
| 9400862 |
Cells having transistors and interconnects including nanowires or 2D material strips |
Jamil Kawa |
2016-07-26 |
| 9379018 |
Increasing Ion/Ioff ratio in FinFETs and nano-wires |
Munkang Choi, Xi-Wei Lin |
2016-06-28 |
| 9378320 |
Array with intercell conductors including nanowires or 2D material strips |
Jamil Kawa |
2016-06-28 |
| 9379183 |
Methods for manufacturing integrated circuit devices having features with reduced edge curvature |
Lars Bomholt |
2016-06-28 |
| 9361418 |
Nanowire or 2D material strips interconnects in an integrated circuit cell |
Jamil Kawa |
2016-06-07 |
| 9287253 |
Method and apparatus for floating or applying voltage to a well of an integrated circuit |
Jamil Kawa, James David Sproch, Robert B. Lefferts |
2016-03-15 |
| 9275182 |
Placing transistors in proximity to through-silicon vias |
James David Sproch, Xiaopeng Xu, Aditya Pradeep Karmarkar |
2016-03-01 |
| 9257429 |
N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch |
Deepak D. Sherlekar |
2016-02-09 |