Issued Patents 2016
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9448879 | Apparatus and method for implement a multi-level memory hierarchy | Oded Lempel, Hisham Shafi, Geeyarpuram N. Santhanakrishnan, Jose A. Vargas, Ganapati Srinivasa +6 more | 2016-09-20 |
| 9405646 | Method and apparatus for injecting errors into memory | Kai Cheng, Mohan J. Kumar, Jose A. Vargas, Gopikrishna Jandhyala | 2016-08-02 |
| 9342394 | Secure error handling | Murugasamy K. Nachimuthu, Mohan J. Kumar, Jose A. Vargas, Rajender Kuramkote | 2016-05-17 |
| 9317360 | Machine check summary register | Jose A. Vargas, Mohan J. Kumar, James B. Crossland, Murugasamy K. Nachimuthu | 2016-04-19 |