Issued Patents 2016
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9514831 | Multi-clock generation through phase locked loop (PLL) reference | Sung-En Wang, Steve Choi, Jongmin Park | 2016-12-06 |
| 9418750 | Single ended word line and bit line time constant measurement | Sung-En Wang, Jongmin Park | 2016-08-16 |
| 9368224 | Self-adjusting regulation current for memory array source line | Sung-En Wang, Steve Choi, Jongmin Park | 2016-06-14 |
| 9330776 | High voltage step down regulator with breakdown protection | Jongmin Park, Trung Pham | 2016-05-03 |
| 9325276 | Methods and apparatus for clock oscillator temperature coefficient trimming | Albert Chang, Jongmin Park | 2016-04-26 |
| 9318209 | Digitally controlled source side select gate offset in 3D NAND memory erase | Maurice Chen, Jongmin Park, Tien-Chien Kuo | 2016-04-19 |