| 9477476 |
Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media |
Melinda J. Brown, Michael William Morrow, James Norris Dieffenderfer, Michael Scott McIlvaine, Rodney Wayne Smith +2 more |
2016-10-25 |
| 9477478 |
Multi level indirect predictor using confidence counter and program counter address filter scheme |
Kulin N. Kothari, Michael William Morrow, James Norris Dieffenderfer, Michael Scott McIlvaine, Daren Eugene Streett |
2016-10-25 |
| 9460018 |
Method and apparatus for tracking extra data permissions in an instruction cache |
Leslie Mark DeBruyne, James Norris Dieffenderfer, Michael Scott McIlvaine |
2016-10-04 |
| 9411590 |
Method to improve speed of executing return branch instructions in a processor |
Rodney Wayne Smith, Jeffery M. Schottmiller, Michael Scott McIlvaine, Melinda J. Brown, Daren Eugene Streett |
2016-08-09 |
| 9329930 |
Cache memory error detection circuits for detecting bit flips in valid indicators in cache memory following invalidate operations, and related methods and processor-based systems |
John Ingalls, Thomas Philip Speier |
2016-05-03 |
| 9317293 |
Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media |
James Norris Dieffenderfer, Michael William Morrow, Michael Scott McIlvaine, Daren Eugene Streett, Vimal Reddy |
2016-04-19 |