Issued Patents 2016
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9389871 | Combined floating point multiplier adder with intermediate rounding logic | Marc Lupon, Grigorios Magklis, Sridhar Samudrala, Raul Martinez, Kyriakos A. Stavrou | 2016-07-12 |
| 9329848 | Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programs | Marc Lupon, Raul Martinez, Kyriakos A. Stavrou, Grigorios Magklis, Sridhar Samudrala | 2016-05-03 |