Issued Patents 2016
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9471088 | Restricting clock signal delivery in a processor | Alexander Gendler, Efraim Rotem, Julius Mandelblat, Alexander Lyakhov, George Leifman +3 more | 2016-10-18 |
| 9471494 | Method and apparatus for cache line write back operation | Rajesh M. Sankaran, Neil Schaper, Joseph Nuzman, Yen-Cheng Liu, Gilbert Neiger +1 more | 2016-10-18 |
| 9448879 | Apparatus and method for implement a multi-level memory hierarchy | Theodros Yigzaw, Oded Lempel, Hisham Shafi, Geeyarpuram N. Santhanakrishnan, Jose A. Vargas +6 more | 2016-09-20 |
| 9378148 | Adaptive hierarchical cache policy in a microprocessor | Joseph Nuzman, Alexander Gendler | 2016-06-28 |
| 9367464 | Cache circuit having a tag array with smaller latency than a data array | — | 2016-06-14 |
| 9360924 | Reduced power mode of a cache unit | Alexander Gendler, Ariel Sabba, Niv Tokman | 2016-06-07 |