Issued Patents 2016
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9472248 | Method and apparatus for implementing a heterogeneous memory subsystem | Alaa R. Alameldeen, Zeshan A. Chishti, Jaewoong Sim | 2016-10-18 |
| 9417879 | Systems and methods for managing reconfigurable processor cores | Alaa R. Alameldeen, Eugene Gorbatov, Zeshan A. Chishti | 2016-08-16 |
| 9378021 | Instruction and logic for run-time evaluation of multiple prefetchers | Zeshan A. Chishti, Seth H. Pugsley, Peng-Fei Chuang, Robert L. Scott, Aamer Jaleel +2 more | 2016-06-28 |
| 9286224 | Constraining prefetch requests to a processor socket | Seth H. Pugsley, Robert L. Scott, Zeshan A. Chishti, Peng-Fei Chuang, Khun Ban +2 more | 2016-03-15 |
| 9229872 | Semiconductor chip with adaptive BIST cache testing during runtime | Jawad Nasrullah, Kelvin Kwan | 2016-01-05 |