Issued Patents 2016
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9404969 | Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies | Brion Keller, Steven M. Douskey | 2016-08-02 |
| 9378318 | Shared channel masks in on-product test compression system | Steven M. Douskey | 2016-06-28 |
| 9372232 | Collecting diagnostic data from chips | Steven M. Douskey, Ryan A. Fitch, William V. Huott | 2016-06-21 |
| 9355203 | Shared channel masks in on-product test compression system | Steven M. Douskey | 2016-05-31 |
| 9297856 | Implementing MISR compression methods for test time reduction | Steven M. Douskey, Cedric Lichtenau | 2016-03-29 |
| 9292399 | Design-Based weighting for logic built-in self-test | Gregory J. Cook, Timothy J. Koprowski, Cedric Lichtenau | 2016-03-22 |
| 9292398 | Design-based weighting for logic built-in self-test | Gregory J. Cook, Timothy J. Koprowski, Cedric Lichtenau | 2016-03-22 |
| 9285423 | Managing chip testing data | Steven M. Douskey, Ryan A. Fitch, William V. Huott | 2016-03-15 |
| 9268892 | Identification of unknown sources for logic built-in self test in verification | Satya R. S. Bhamidipati, Cedric Lichtenau, Srinivas V. N. Polisetty | 2016-02-23 |