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Writing multiple levels in a phase change memory |
Scott C. Lewis, Thomas M. Maffitt, Jack Morrish |
2016-11-22 |
| 9478736 |
Structure and fabrication of memory array with epitaxially grown memory elements and line-space patterns |
John K. DeBrosse, Janusz J. Nowak |
2016-10-25 |
| 9343545 |
Electrical coupling of memory cell access devices to a word line |
Jing Li, Edward W. Kiewra |
2016-05-17 |
| 9311009 |
Memory with mixed cell array and system including the memory |
Bing Dai, Jing Li |
2016-04-12 |
| 9298383 |
Memory with mixed cell array and system including the memory |
Bing Dai, Jing Li |
2016-03-29 |
| 9299804 |
Electrical coupling of memory cell access devices to a word line |
Jing Li, Edward W. Kiewra |
2016-03-29 |
| 9299431 |
Writing multiple levels in a phase change memory using a write/read reference voltage ramping up over a write/read period |
Scott C. Lewis, Thomas M. Maffitt, Jack Morrish |
2016-03-29 |
| 9276208 |
Phase change memory cell with heat shield |
Matthew J. BrightSky, Alejandro G. Schrott |
2016-03-01 |
| 9269042 |
Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices |
Daniel J. Friedman, Seongwon Kim, Dharmendra S. Modha, Bipin Rajendran, Jose A. Tierno |
2016-02-23 |
| 9269435 |
Drift mitigation for multi-bits phase change memory |
Jing Li |
2016-02-23 |
| 9263336 |
Symmetrical bipolar junction transistor array |
Matthew J. BrightSky, Jin Cai, Sangbum Kim, Tak H. Ning |
2016-02-16 |
| 9257639 |
Phase-change memory cells |
Sangbum Kim, Daniel Krebs, Charalampos Pozidis |
2016-02-09 |
| 9250816 |
Adaptive reference tuning for endurance enhancement of non-volatile memories |
Bing Dai, Jing Li |
2016-02-02 |
| 9245619 |
Memory device with memory buffer for premature read protection |
Kyu-hyoun Kim, Sangbum Kim |
2016-01-26 |
| 9240324 |
Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor |
Matthew J. BrightSky, Gen P. Lauer |
2016-01-19 |
