Issued Patents 2016
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9529406 | System interconnect dynamic scaling by lane width and operating frequency balancing | Daniel M. Dreps, Frank D. Ferraiolo, Prasanna Jayaraman | 2016-12-27 |
| 9524013 | System interconnect dynamic scaling by lane width and operating frequency balancing | Daniel M. Dreps, Frank D. Ferraiolo, Prasanna Jayaraman | 2016-12-20 |
| 9471239 | Memory power management and data consolidation | Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Arun Joseph | 2016-10-18 |
| 9471540 | Detecting TSV defects in 3D packaging | Edgar R. Cordero, Girisankar Paulraj, Diyanesh B. Vidyapoornachary | 2016-10-18 |
| 9460251 | Formal verification driven power modeling and design verification | Arun Joseph, Pradeep Kumar Nalla, Rahul M. Rao | 2016-10-04 |
| 9459982 | Bus interface optimization by selecting bit-lanes having best performance margins | Daniel M. Dreps, Frank D. Ferraiolo, Prasanna Jayaraman | 2016-10-04 |
| 9324031 | System interconnect dynamic scaling by predicting I/O requirements | Daniel M. Dreps, Frank D. Ferraiolo, Prasanna Jayaraman, David J. Krolak | 2016-04-26 |
| 9324030 | System interconnect dynamic scaling by predicting I/O requirements | Daniel M. Dreps, Frank D. Ferraiolo, Prasanna Jayaraman, David J. Krolak | 2016-04-26 |
| 9252131 | Chip stack cache extension with coherency | Edgar R. Cordero, Subrat K. Panda, Saravanan Sethuraman, Diyanesh Babu C. Vidyapoornachary | 2016-02-02 |
| 9244799 | Bus interface optimization by selecting bit-lanes having best performance margins | Daniel M. Dreps, Frank D. Ferraiolo, Prasanna Jayaraman | 2016-01-26 |