Issued Patents 2016
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9425139 | Dual row quad flat no-lead semiconductor package | Chenglin Liu, Sheng C. Liao | 2016-08-23 |
| 9391045 | Recessed semiconductor substrates and associated techniques | Albert Wu, Roawen Chen, Chung Chyung Han, Chien-Chuan Wei, Runzi Chang +2 more | 2016-07-12 |
| 9355951 | Interconnect layouts for electronic assemblies | Huahung Kao | 2016-05-31 |
| 9331052 | Pad configurations for an electronic package assembly | Sehat Sutardja, Huahung Kao | 2016-05-03 |
| 9288909 | Ball grid array package substrate with through holes and method of forming same | Chenglin Liu | 2016-03-15 |
| 9275929 | Package assembly having a semiconductor substrate | Sehat Sutardja, Albert Wu, Chuan-Cheng Cheng, Chien-Chuan Wei | 2016-03-01 |
| 9257410 | Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate | Albert Wu, Roawen Chen, Chung Chyung Han, Chien-Chuan Wei, Runzi Chang +2 more | 2016-02-09 |
| 9252115 | Method for forming semiconductor layout | Thomas Ngo | 2016-02-02 |
| 9240372 | Semiconductor die having lead wires formed over a circuit in a shielded area | — | 2016-01-19 |