ET

Erwin Trautmann

AI Atomera Incorporated: 1 patents #1 of 3Top 35%
MT Mears Technologies: 1 patents #1 of 3Top 35%
📍 San Jose, CA: #1,407 of 5,790 inventorsTop 25%
🗺 California: #12,284 of 57,791 inventorsTop 25%
Overall (2016): #144,692 of 481,213Top 35%
2
Patents 2016

Issued Patents 2016

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
9406753 Semiconductor devices including superlattice depletion layer stack and related methods Robert J. Mears, Hideki Takeuchi 2016-08-02
9275996 Vertical semiconductor devices including superlattice punch through stop layer and related methods Robert J. Mears, Hideki Takeuchi 2016-03-01