Issued Patents 2016
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 9529533 | Power grid segmentation for memory arrays | Michael A. Dreesen, Naveen Javarappa, Ajay Bhatia | 2016-12-27 | $55,003,000 |
| 9455000 | Shared gate fed sense amplifier | Ramesh Arvapalli | 2016-09-27 | $72,288,000 |
| 9389635 | Selectable phase or cycle jitter detector | James E. Burnette, II | 2016-07-12 | $81,101,000 |
| 9311967 | Configurable voltage reduction for register file | Ajay Bhatia, Anshul Y. Mehta, Amrinder S. Barn | 2016-04-12 | $59,139,000 |
| 9286971 | Method and circuits for low latency initialization of static random access memory | Ramesh Arvapalli, Andrew L. Arengo | 2016-03-15 | $68,647,000 |
| 9236100 | Dynamic global memory bit line usage as storage node | Ramesh Arvapalli | 2016-01-12 | $83,071,000 |
| 9230690 | Register file write ring oscillator | James E. Burnette, II | 2016-01-05 | $62,283,000 |