Issued Patents 2016
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9430243 | Optimizing register initialization operations | James B. Keller, John H. Mylius, Conrado Blasco-Allue | 2016-08-30 |
| 9418010 | Global maintenance command protocol in a cache coherent system | Stephan G. Meier | 2016-08-16 |
| 9383806 | Multi-core processor instruction throttling | Wei-Han Lien, Rohit Kumar, Sandeep Gupta, Suresh Periyacheri, Shih-Chieh Wen | 2016-07-05 |
| 9336003 | Multi-level dispatch for a superscalar processor | John H. Mylius, Shyam Balasubramanian, Conrado Blasco-Allue | 2016-05-10 |
| 9317285 | Instruction set architecture mode dependent sub-size access of register with associated status indication | Sandeep Gupta, Conrado Blasco-Allue, John H. Mylius, James B. Keller | 2016-04-19 |
| 9311100 | Usefulness indication for indirect branch prediction training | Sandeep Gupta, Shyam Sundar, Wei-Han Lien, Conrado Blasco-Allue | 2016-04-12 |
| 9280471 | Mechanism for sharing private caches in a SoC | Manu Gulati, Harshavardhan Kaushikkar, Gurjeet S. Saund, Wei-Han Lien, Sukalpa Biswas +2 more | 2016-03-08 |