Issued Patents 2011
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8051247 | Trace based deallocation of entries in a versioning cache circuit | Paul G. Chan, Graham Ricketson Murphy, Joseph B. Rowlands | 2011-11-01 |
| 8037285 | Trace unit | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar, Matthew William Ashcraft, Ivan Pavle Radivojevic | 2011-10-11 |
| 8032710 | System and method for ensuring coherency in trace execution | Matthew William Ashcraft, Joseph B. Rowlands, Leonard Eric Shar, Richard Win Thaik | 2011-10-04 |
| 8024522 | Memory ordering queue/versioning cache circuit | Paul G. Chan, Graham Ricketson Murphy, Joseph B. Rowlands | 2011-09-20 |
| 8019944 | Checking for a memory ordering violation after a speculative cache write | Paul G. Chan, Graham Ricketson Murphy, Joseph B. Rowlands | 2011-09-13 |
| 8015359 | Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit | Joseph B. Rowlands, Leonard Eric Shar, Richard Win Thaik | 2011-09-06 |
| 8010745 | Rolling back a speculative update of a non-modifiable cache line | Paul G. Chan, Graham Ricketson Murphy, Joseph B. Rowlands | 2011-08-30 |
| 7987342 | Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar | 2011-07-26 |
| 7966479 | Concurrent vs. low power branch prediction | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar | 2011-06-21 |
| 7953961 | Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar | 2011-05-31 |
| 7953933 | Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar | 2011-05-31 |
| 7949854 | Trace unit with a trace builder | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar | 2011-05-24 |
| 7941607 | Method and system for promoting traces in an instruction processing circuit | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar, Matthew William Ashcraft | 2011-05-10 |
| 7937564 | Emit vector optimization of a trace | Matthew William Ashcraft, Christopher Patrick Nelson, Ivan Pavle Radivojevic, Joseph B. Rowlands, Richard Win Thaik | 2011-05-03 |
| 7877630 | Trace based rollback of a speculatively updated cache | Paul G. Chan, Graham Ricketson Murphy, Joseph B. Rowlands | 2011-01-25 |
| 7870369 | Abort prioritization in a trace-based processor | Christopher Patrick Nelson, Richard Win Thaik | 2011-01-11 |