Issued Patents 2011
Showing 51–71 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7925942 | Augmentation instruction shift register with serial and two parallel inputs | Baher Haroun | 2011-04-12 |
| 7917824 | Scan path adaptor with state machine, counter, and gate circuitry | — | 2011-03-29 |
| 7917822 | Serial I/O using JTAG TCK and TMS signals | — | 2011-03-29 |
| 7913135 | Interconnections for plural and hierarchical P1500 test wrappers | — | 2011-03-22 |
| 7908537 | Boundary scan path method and system with functional and non-functional scan cell memories | — | 2011-03-15 |
| 7904774 | Wafer scale testing using a 2 signal JTAG interface | — | 2011-03-08 |
| 7900110 | Optimized JTAG interface | — | 2011-03-01 |
| 7890829 | Reduced signaling interface method and apparatus | — | 2011-02-15 |
| 7890825 | Data summing boundary cell | — | 2011-02-15 |
| 7877650 | Core circuit test architecture | — | 2011-01-25 |
| 7877658 | IEEE 1149.1 and P1500 test interfaces combined circuits and processes | — | 2011-01-25 |
| 7877654 | Selectable JTAG or trace access with data store and output | — | 2011-01-25 |
| 7877653 | Address and TMS gating circuitry for TAP control circuit | — | 2011-01-25 |
| 7877651 | Dual mode test access port method and apparatus | — | 2011-01-25 |
| 7876112 | Parallel scan distributors and collectors and process of testing integrated circuits | — | 2011-01-25 |
| 7873889 | JTAG bus communication method and apparatus | — | 2011-01-18 |
| 7870450 | High speed double data rate JTAG interface | — | 2011-01-11 |
| 7870451 | Automatable scan partitioning for low power using external control | Jayashree Saxena | 2011-01-11 |
| 7863919 | Applying test response start and command signals to power lead | — | 2011-01-04 |
| 7865791 | Reduced signaling interface method and apparatus | — | 2011-01-04 |
| 7863913 | Parallel scan distributors and collectors and process of testing integrated circuits | — | 2011-01-04 |