Issued Patents 2011
Showing 26–50 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7996740 | Adaptor With Clocks For Like Parts of Different Scan Paths | — | 2011-08-09 |
| 7984349 | IC multiplexer control circuitry for tap selection circuitry | — | 2011-07-19 |
| 7984331 | TAM with scan frame copy register coupled with serial output | — | 2011-07-19 |
| 7975196 | Resynchronization memory in series/parallel with control/data scan cells | — | 2011-07-05 |
| 7965103 | Quad to binary converter with directly connected and coupled outputs | — | 2011-06-21 |
| 7962812 | Scan controller control input to sequential core without scan path | — | 2011-06-14 |
| 7962813 | 1149.1 tap linking modules | Baher Haroun, Brian J. Lasher, Anjali Kinra | 2011-06-14 |
| 7962815 | Tap demultiplexer with select and select one outputs for HTML | — | 2011-06-14 |
| 7962816 | I/O switches and serializer for each parallel scan register | — | 2011-06-14 |
| 7962817 | IEEE 1149.1 and P1500 test interfaces combined circuits and processes | — | 2011-06-14 |
| 7962818 | Reduced signaling interface method and apparatus | — | 2011-06-14 |
| 7956357 | Test pads coupled with leads unconnected with die pads | Richard L. Antley | 2011-06-07 |
| 7958420 | Clock delay circuits and multiplexer connected to boundary scan circuitry | — | 2011-06-07 |
| 7954030 | Automatable scan partitioning for low power using external control | Jayashree Saxena | 2011-05-31 |
| 7954024 | Selecting scan test/TAP with FF receiving lock in and update-IR | — | 2011-05-31 |
| 7954027 | Reduced signaling interface method and apparatus | — | 2011-05-31 |
| 7954026 | TAM controller connected with TAM and functional core wrapper circuit | — | 2011-05-31 |
| 7945832 | Interface to full and reduced pin JTAG devices | — | 2011-05-17 |
| 7937635 | Selectively accessing test access ports in a multiple test access port environment | — | 2011-05-03 |
| 7937637 | TAP with enable input gated and multiplexed mode select | — | 2011-05-03 |
| 7936183 | IC output signal path with switch, bus holder, and buffer | — | 2011-05-03 |
| 7925943 | Multiplexer connecting TDI or AX1/TDI to data and instruction registers | — | 2011-04-12 |
| 7925951 | Scan circuitry controlled switch connecting buffer output to test lead | — | 2011-04-12 |
| 7925946 | DDR gate and delay clock circuitry for parallel interface registers | — | 2011-04-12 |
| 7925945 | Generator/compactor scan circuit low power adapter | — | 2011-04-12 |