Issued Patents 2011
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8086990 | Method of correlating silicon stress to device instance parameters for circuit simulation | Victor Moroz, Dipankar Pramanik | 2011-12-27 |
| 8069430 | Stress-managed revision of integrated circuit layouts | Victor Moroz, Dipankar Pramanik | 2011-11-29 |
| 8035168 | Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance | Victor Moroz, Dipankar Pramanik | 2011-10-11 |
| 7949985 | Method for compensation of process-induced performance variation in a MOSFET integrated circuit | Victor Moroz, Dipankar Pramanik, Kishore Singhal | 2011-05-24 |
| 7926018 | Method and apparatus for generating a layout for a transistor | Victor Moroz, Mark Rubin | 2011-04-12 |
| 7908573 | Minimizing effects of interconnect variations in integrated circuit designs | — | 2011-03-15 |
| 7897479 | Managing integrated circuit stress using dummy diffusion regions | Dipankar Pramanik, Victor Moroz | 2011-03-01 |
| 7895548 | Filler cells for design optimization in a place-and-route system | Jyh Chwen Frank Lee, Dipankar Pramanik | 2011-02-22 |
| 7863146 | Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance | Victor Moroz, Dipankar Pramanik | 2011-01-04 |