Issued Patents 2011
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8076779 | Reduction of macro level stresses in copper/low-K wafers | Sey-Shing Sun, Jayanthi Pallinti, Dilip Vijay, Hong Ying, Chiyi Kao +1 more | 2011-12-13 |
| 7955919 | Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemes | David Pritchard, David T. Price | 2011-06-07 |
| 7915122 | Self-aligned cell integration scheme | Richard J. Carter, Shiqun Gu, Peter A. Burke, James R. B. Elmer, Sey-Shing Sun +2 more | 2011-03-29 |