Issued Patents 2011
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8019566 | System and method for efficiently testing cache congruence classes during processor design verification and validation | Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Shakti Kapoor, Batchu Naga Venkata Satyanarayana | 2011-09-13 |
| 8006221 | System and method for testing multiple processor modes for processor design verification and validation | Sampan Arora, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Shakti Kapoor, Sai Rupak Mohanan | 2011-08-23 |
| 7992059 | System and method for testing a large memory area during processor design verification and validation | Divya S. Anvekar, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Shakti Kapoor | 2011-08-02 |
| 7966521 | Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics | Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor | 2011-06-21 |