Issued Patents 2011
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8030649 | Scan testing in single-chip multicore systems | — | 2011-10-04 |
| 8010953 | Method for compiling scalar code for a single instruction multiple data (SIMD) execution engine | — | 2011-08-30 |
| 8006070 | Method and apparatus for inhibiting fetch throttling when a processor encounters a low confidence branch instruction in an information handling system | Robert Alan Philhower, Raymond Cheung Yeung | 2011-08-23 |
| 7987464 | Logical partitioning and virtualization in a heterogeneous architecture | Michael Norman Day, Mark Richard Nutter, James Xenidis | 2011-07-26 |
| 7977965 | Soft error detection for latches | Bruce M. Fleischer | 2011-07-12 |
| 7925853 | Method and apparatus for controlling memory array gating when a processor executes a low confidence branch instruction in an information handling system | Robert Alan Philhower, Raymond Cheung Yeung | 2011-04-12 |
| 7900025 | Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations | — | 2011-03-01 |
| 7877759 | System for efficient performance monitoring of a large number of simultaneous events | Alan Gara, Valentina Salapura | 2011-01-25 |
| 7877582 | Multi-addressable register file | Brett Olsson | 2011-01-25 |
| 7865693 | Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type | Alexandre E. Eichenberger, Bruce M. Fleischer | 2011-01-04 |
| 7865699 | Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code | Erik R. Altman, David Arnold Luick, Daniel A. Prener, Jude A. Rivers, Sumedh W. Sathaye +1 more | 2011-01-04 |