Issued Patents 2011
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8019968 | 3-dimensional L2/L3 cache array to hide translation (TLB) delays | — | 2011-09-13 |
| 8019969 | Self prefetching L3/L4 cache mechanism | — | 2011-09-13 |
| 8001361 | Structure for a single shared instruction predecoder for supporting multiple processors | — | 2011-08-16 |
| 7996655 | Multiport execution target delay queue FIFO array | — | 2011-08-09 |
| 7996654 | System and method for optimization within a group priority issue schema for a cascaded pipeline | — | 2011-08-09 |
| 7984270 | System and method for prioritizing arithmetic instructions | — | 2011-07-19 |
| 7984272 | Design structure for single hot forward interconnect scheme for delayed execution pipelines | — | 2011-07-19 |
| 7945763 | Single shared instruction predecoder for supporting multiple processors | — | 2011-05-17 |
| 7941654 | Local and global branch prediction information storage | — | 2011-05-10 |
| 7937530 | Method and apparatus for accessing a cache with an effective address | — | 2011-05-03 |
| 7882335 | System and method for the scheduling of load instructions within a group priority issue schema for a cascaded pipeline | — | 2011-02-01 |
| 7877579 | System and method for prioritizing compare instructions | — | 2011-01-25 |
| 7870368 | System and method for prioritizing branch instructions | — | 2011-01-11 |
| 7865700 | System and method for prioritizing store instructions | — | 2011-01-04 |
| 7865769 | In situ register state error recovery and restart mechanism | — | 2011-01-04 |
| 7865699 | Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code | Erik R. Altman, Michael K. Gschwind, Daniel A. Prener, Jude A. Rivers, Sumedh W. Sathaye +1 more | 2011-01-04 |