Issued Patents 2011
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8086429 | Predicate-based compositional minimization in a verification environment | Jason R. Baumgartner, Viresh Paruthi, Fadi A. Zaraket | 2011-12-27 |
| 8042075 | Method, system and application for sequential cofactor-based analysis of netlists | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2011-10-18 |
| 8037085 | Predicate selection in bit-level compositional transformations | Jason R. Baumgartner, Viresh Paruthi, Fadi Z. Zaraket | 2011-10-11 |
| 8015528 | Enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2011-09-06 |
| 8015523 | Method and system for sequential netlist reduction through trace-containment | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2011-09-06 |
| 7996800 | Computer program product for design verification using sequential and combinational transformations | Jason Raymond Baumgarter, Robert L. Kanzelman, Viresh Paruthi | 2011-08-09 |
| 7996803 | Automated use of uninterpreted functions in sequential equivalence | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2011-08-09 |
| 7934180 | Incremental speculative merging | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2011-04-26 |
| 7930672 | Incremental design reduction via iterative overapproximation and re-encoding strategies | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2011-04-19 |
| 7921394 | Enhanced verification through binary decision diagram-based target decomposition | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2011-04-05 |
| 7917874 | Reversing the effects of sequential reparameterization on traces | Jason R. Baumgartner, Geert Janssen, Viresh Paruthi | 2011-03-29 |
| 7917884 | Enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2011-03-29 |
| 7913218 | Reduction of XOR/XNOR subexpressions in structural design representations | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2011-03-22 |
| 7913208 | Optimal simplification of constraint-based testbenches | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2011-03-22 |
| 7913205 | Method and system for reversing the effects of sequential reparameterization on traces | Jason R. Baumgartner, Geert Janssen, Viresh Paruthi | 2011-03-22 |
| 7908575 | Enhanced verification through binary decision diagram-based target decomposition using state analysis extraction | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2011-03-15 |
| 7890901 | Method and system for verifying the equivalence of digital circuits | Tobias Gemmeke, Jens Leenstra, Nicolas Maeding | 2011-02-15 |
| 7882470 | Method for heuristic preservation of critical inputs during sequential reparameterization | Jason R. Baumgartner, Geert Janssen, Viresh Paruthi | 2011-02-01 |
| 7882473 | Sequential equivalence checking for asynchronous verification | Jason R. Baumgartner, Yee Ja, Viresh Paruthi, Barinjato Ramanandray | 2011-02-01 |
| 7882459 | Method and system for reduction of AND/OR subexpressions in structural design representations | Jason R. Baumgartner, Robert L. Kanzelman, Viresh Paruthi | 2011-02-01 |