Issued Patents 2011
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8006213 | Optimization method of integrated circuit design for reduction of global clock load and balancing clock skew | Christopher J. Berry, Jose L. Neves, David W. Lewis | 2011-08-23 |
| 7941689 | Minimizing clock uncertainty on clock distribution networks using a multi-level de-skewing technique | Jose Neves, Phillip J. Restle | 2011-05-10 |